ATMEGA169P-16MCHR【PDF 106/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

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Sheet目录3753

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PIC16F946

DS41265A-page 192

Preliminary

2005 Microchip Technology Inc.

16.1

Configuration Bits

The configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 16-1.

These bits are mapped in program memory location

2007h.

REGISTER 16-1:

CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)

Note:

Address

2007h is

beyond the user

program memory space. It belongs to the

special

configuration

memory

space

(2000h-3FFFh), which can be accessed

only

during

programming.

See

“PIC16F91X/946 Memory Programming

Specification”

(DS41244)

for

information.

—DEBUG

FCMEN

IESO

BOREN1

BOREN0

CPD

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

bit 13

bit 0

bit 13

Unimplemented: Read as ‘1’

bit 12

DEBUG: In-Circuit Debugger Mode bit

= In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins

= In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger

bit 11

FCMEN: Fail-Safe Clock Monitor Enabled bit

= Fail-Safe Clock Monitor is enabled

= Fail-Safe Clock Monitor is disabled

bit 10

IESO: Internal External Switchover bit

= Internal External Switchover mode is enabled

= Internal External Switchover mode is disabled

bit 9-8

BOREN<1:0>: Brown-out Reset Selection bits(1)

= BOR enabled

= BOR enabled during operation and disabled in Sleep

= BOR controlled by SBOREN bit (PCON<4>)

= BOR disabled

bit 7

CPD: Data Code Protection bit(2)

= Data memory code protection is disabled

= Data memory code protection is enabled

bit 6

CP: Code Protection bit(3)

= Program memory code protection is disabled

= Program memory code protection is enabled

bit 5

MCLRE: RB3/MCLR/VPP pin function select bit(4)

= RB3/MCLR/VPP pin function is MCLR

= RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD

bit 4

PWRTE: Power-up Timer Enable bit

= PWRT disabled

= PWRT enabled

bit 3

WDTE: Watchdog Timer Enable bit

= WDT enabled

= WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)

bit 2-0

FOSC<2:0>: Oscillator Selection bits

111

= RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI

110

= RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI

101

= INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI

100

= INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI

011

= EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI

010

= HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

001

= XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

000

= LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

Note

Enabling Brown-out Reset does not automatically enable Power-up Timer.

The entire data EEPROM will be erased when the code protection is turned off.

The entire program memory will be erased when the code protection is turned off.

When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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